The present invention relates to a semiconductor device technology and, particularly to a technology which is effective when applied to a semiconductor device having transistors in which gate insulating films have different thicknesses.
In semiconductor devices, there are used integrated circuits each formed of elements having various characteristics, formed over a semiconductor substrate, and electrically coupled to each other with wiring. Integrated circuits include a logic circuit for control, a driving circuit, a memory circuit for storing information, and the like. To allow these integrated circuits to perform desired functions, types of semiconductor elements forming the integrated circuits, a wiring method, and the like are designed.
Examples of the semiconductor elements forming the integrated circuits include a field effect transistor (FET), and the like. The field effect transistor mostly has a metal insulator semiconductor (MIS) structure in which a gate electrode is formed over a semiconductor substrate via an insulating film. Note that, in the case of using a silicon dioxide film or the like as the insulating film, the resulting structure is called a metal oxide semiconductor (MOS) structure. Such MIS field effect transistors (hereinafter simply referred to as MIS transistors) are covered with an interlayer insulating film over the semiconductor substrate, and individually insulated. In addition, contact plugs are formed so as to extend through the interlayer insulating film to be electrically coupled to the terminals of the semiconductor elements. Over the interlayer insulating film, such metal wires as to electrically couple the desired contact plugs to each other are formed.
Examples of semiconductor devices examined by the present inventors include an LCD driver which is a driving semiconductor device for causing a liquid crystal display (LCD) to perform a display operation. The LCD driver has integrated circuits having various functions such as an operation control circuit, a main memory circuit, a nonvolatile memory circuit, and a power source control circuit which are mounted over one chip. Thus, the LCD driver is formed of MIS transistors having various characteristics. In particular, there are a MIS transistor which satisfies a high-speed-operation requirement, a MIS transistor which satisfies a high-breakdown-voltage requirement, a MIS transistor which serves as a component of a nonvolatile memory, and the like.
The MIS transistors that satisfy the respective requirements shown above have gate insulating films of different thicknesses. Qualitatively, a MIS transistor having a thinner gate insulating film is capable of higher-speed operation, while a MIS transistor having a thicker gate insulating film is capable of operation with a higher voltage. In the LCD driver examined by the present inventors, MIS transistors having gate insulating films which differ in thickness in the range of 2 to 100 nm are used in accordance with required characteristics. As a result, the LCD driver examined by the present inventors has a structure including gates of different heights over a semiconductor substrate.
For example, in Japanese Unexamined Patent Publication No. 2004-235313 (Patent Document 1), a technology is disclosed which forms a bird's beak of a desired size in each of the end portions of a gate insulating film covering an active region defined by an isolation portion. This allows the provision of a semiconductor device having a gate insulating film with excellent electrical characteristics.
For example, in Japanese Unexamined Patent Publication No. 2005-197652 (Patent Document 2), a technology is disclosed which forms an oxide film for high-voltage element in a high-voltage-element region, and then adjusts a pad-nitride-film strip step in a low-voltage-element/cell region to reduce the height of the oxide film for high-voltage element. This allows a reduction in the level difference between the high-voltage-element region and the low-voltage-element/cell region.
In Japanese Unexamined Patent Publication No. 2008-16499 (Patent Document 3), a technology is disclosed which performs a plasma nitridation process to inhibit the thermal oxidation a second region by a predetermined thermal oxidation process performed in a region of a semiconductor substrate located in a second region, and thereby promoting the thermal oxidation of a first region by a predetermined thermal oxidation process performed in a region of the semiconductor substrate located in the first region to a position deeper than that reached by the thermal oxidation of the second region. As a result, the position of the upper surface of a first oxide film becomes closer to that of the upper surface of a second oxide film thinner than the first oxide film, and the level difference between the first region and the second region can be significantly reduced.